Packaged multi-chip semiconductor devices and methods of fabricating same
US11552033B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Jan 22, 2021 |
| Grant date | Jan 10, 2023 |
| Priority date | — |
| Expiry date | Jan 22, 2041 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L2225/1035
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A semiconductor package includes a first connection structure, a first semiconductor chip on an upper surface of the first connection structure, a first molding layer on the upper surface of the first connection structure and surrounding the first semiconductor chip, a first bond pad on the first semiconductor chip, a first bond insulation layer on the first semiconductor chip and the first molding layer and surrounding the first bond pad, a second bond pad directly contacting the first bond pad, a second bond insulation layer surrounding the second bond pad; and a second semiconductor chip on the second bond pad and the second bond insulation layer.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.