Strap-cell architecture for embedded memory
US11552087B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Mar 3, 2021 |
| Grant date | Jan 10, 2023 |
| Priority date | — |
| Expiry date | May 29, 2041 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D64/661
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
Various embodiments of the present application are directed towards an integrated memory chip comprising a memory array with a strap-cell architecture that reduces the number of distinct strap-cell types and that reduces strap-line density. In some embodiments, the memory array is limited to three distinct types of strap cells: a source line/erase gate (SLEG) strap cell; a control gate/word line (CGWL) strap cell; and a word-line strap cell. The small number of distinct strap-cell types simplifies design of the memory array and further simplifies design of a corresponding interconnect structure. Further, in some embodiments, the three distinct strap-cell types electrically couple word lines, erase gates, and control gates to corresponding strap lines in different metallization layers of an interconnect structure. By spreading the strap lines amongst different metallization layers, strap-line density is reduced.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.