Low loss power device and method for fabricating thereof
US11552194B2 · kind B2 · utility
Assignee
Inventor
Key dates
| Filing date | Feb 19, 2021 |
| Grant date | Jan 10, 2023 |
| Priority date | — |
| Expiry date | Feb 19, 2041 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D64/516
Abstract
Existing semiconductor transistor processes may be leveraged to form lateral extensions adjacent to a conventional gate structure. The dielectric thickness under these lateral gate extensions can be varied to optimize device channel resistance and enable resistance to breakdown at high operating voltages. These extensions may be patterned with dimensions that are not limited by lithographic resolution and overlay capabilities and are compatible with conventional processing for ease of integration with other devices. The lateral extensions and dielectric spacers may be used to form self-aligned source, drain, and channel regions. A thin dielectric layer may be formed under an extension gate to reduce channel resistance. A thick dielectric layer may be formed under an extension gate to improve operation voltage range. The present invention provides an innovative structure with lateral gate extensions which may be referred to as EGMOS (extended gate metal oxide semiconductor).
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.