Clock synchronization in half-duplex communication systems
US11552775B1 · kind B1 · utility
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20Claims
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Key dates
| Filing date | Mar 16, 2021 |
| Grant date | Jan 10, 2023 |
| Priority date | — |
| Expiry date | Apr 16, 2041 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH04L7/0037
- WIPO fieldDigital communication
- WIPO sectorElectrical engineering
Abstract
Disclosed are systems, methods, and non-transitory computer-readable media for clock synchronization in half-duplex communication systems. Devices in a half-duplex system are synchronized based on time stamp values captured by each device that define a specified period of time that is of equal in length. The specified period of time spans two change-over periods to average the jitter and/or drift that occurs during each period. Each device uses these measured lengths to determine the variance in the rates at which the two internal clocks operates, which is then used to synchronizes the internal clocks of the two devices.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.