Memory controller, memory device and storage device
US11556415B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Aug 9, 2021 |
| Grant date | Jan 17, 2023 |
| Priority date | — |
| Expiry date | Aug 9, 2041 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06N5/01
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A memory device may determine cell count information from a threshold voltage distribution of memory cells and may determine a detection case based on the cell count information when an error in read data, received from the memory device performing a read operation is not corrected. A memory controller may control the memory device to execute a read operation using a development time determined in consideration of an offset voltage of a read voltage corresponding to the detection case. When an error in the read data is successfully corrected, the memory controller may update a table, stored in the memory controller, using a dynamic offset voltage obtained by inputting the cell count information to a machine learning model.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.