Enhanced word line stripe erase abort detection
US11557348B1 · kind B1 · utility
Assignee
Inventors
Key dates
| Filing date | Jun 24, 2021 |
| Grant date | Jan 17, 2023 |
| Priority date | — |
| Expiry date | Jun 24, 2041 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C16/26
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
Storage devices include a memory array comprised of a plurality of memory devices arranged in word lines. The word lines are further arranged within memory blocks. When erasing memory blocks, various storage devices may utilize a stripe-erase process that alternates the erasure of word lines within the memory blocks. The stripe-erase process is often carried out in multiple steps. However, an ungraceful shutdown can interrupt the erasing processing between one of these stripe-erase steps. The status of each memory device associated with the aborted erasure needs to be known before operations can continue. Methods and systems described herein properly classify and process memory blocks after an aborted erase command by analyzing both even and odd word lines within each of the memory blocks. By properly categorizing each memory block, overprogramming and other negative effects can be avoided, increasing the overall lifespan of the storage device that utilizes a stripe-erase process.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.