Semiconductor device having a capping pattern on a gate electrode
US11557656B2 · kind B2 · utility
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10References
19Claims
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Key dates
| Filing date | Sep 18, 2020 |
| Grant date | Jan 17, 2023 |
| Priority date | — |
| Expiry date | Sep 18, 2040 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D84/83
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
Disclosed are semiconductor devices and methods of manufacturing the same. The semiconductor device comprises a gate electrode on a substrate, an upper capping pattern on the gate electrode, and a lower capping pattern between the gate electrode and the upper capping pattern. The lower capping pattern comprises a first portion between the gate electrode and the upper capping pattern, and a plurality of second portions extending from the first portion onto corresponding side surfaces of the upper capping pattern. The upper capping pattern covers a topmost surface of each of the second portions.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.