Voltage adjust circuit and operation method thereof

US11558043B2 · kind B2 · utility

Assignee

• Au Optronics Corporation · TW

Inventors

• Yi-Chen Lu · Taoyuan, TW
• Hsu-Chi Li · Jinshanmian, TW
• Yi-Jan Chen · Jinshanmian, TW
• Boy-Yiing Jaw · Jinshanmian, TW
• Chin-Tang Chuang · Baoshan, TW
• Chung-Hung Chen · Hsinchu, TW

Key dates

• Filing date: Nov 2, 2021
• Grant date: Jan 17, 2023
• Expiry date: Nov 2, 2041

Classification

• Technology area (CPC H): Electricity
• CPC primary: H03K19/017509
• WIPO field: Basic communication processes
• WIPO sector: Electrical engineering

Abstract

The disclosure provides a voltage adjust circuit. The voltage adjust circuit includes a buffer circuit, a bias circuit, a level shifter and a cross voltage limit circuit. The buffer circuit includes a plurality of pull-up transistors and a plurality of pull-down transistors. The pull-up transistors coupled in series between an output terminal of the circuit and a high voltage system terminal. The pull-down transistors coupled in series between the output terminal and a low voltage system terminal. The cross voltage limit circuit is configured to limit transient and static bias voltages across two terminals of the pull-up transistors or the pull-down transistors.