NVMEoF flow control from initiator based on transaction latency
US11561698B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Apr 20, 2021 |
| Grant date | Jan 24, 2023 |
| Priority date | — |
| Expiry date | Apr 20, 2041 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F15/17331
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A storage array that uses NVMEoF to interconnect compute nodes with NVME SSDs via a fabric and NVME offload engines implements flow control based on transaction latency. Transaction latency is the elapsed time between the send side completion message and receive side completion message for a single transaction. Counts of total transactions and over-latency-limit transactions are accumulated over a time interval. If the over limit rate exceeds a threshold, then the maximum allowed number of enqueued pending transactions is reduced. The maximum allowed number of enqueued pending transactions is periodically restored to a default value.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.