System and method for device mismatch contribution computation for non-continuous circuit outputs
US11562110B1 · kind B1 · utility
Assignee
Inventors
Key dates
| Filing date | Sep 30, 2019 |
| Grant date | Jan 24, 2023 |
| Priority date | — |
| Expiry date | Sep 5, 2041 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F2119/02
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A system, method, and computer program product for predicting mismatch contribution in an electronic environment. Embodiments may include modeling, using a processor, a discrete output mismatch contribution problem using sparse logistic regression to generate a mismatch contribution model and applying a cross-validation approach to increase a complexity of the mismatch contribution model. Embodiments may further include computing one or more mismatch contribution values from the mismatch contribution model and defining at least one sizing constraint or determining a worst case result associated with a sampling process based upon, at least in part, the one or more mismatch contribution values.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.