Detecting deviations from targeted design performance in accelerator/emulator environment
US11562116B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Jul 7, 2020 |
| Grant date | Jan 24, 2023 |
| Priority date | — |
| Expiry date | May 27, 2041 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F30/333
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
Embodiments of the present disclosure provide a method, a system, and a computer readable storage medium for detecting deviations from targeted design performance in accelerator/emulator environment. In an embodiment, the method comprises loading target vales for a performance metric onto a hardware-accelerated simulator; setting breakpoints to pause the simulator at defined intervals; simulating, by the hardware-accelerated simulator, execution of a circuit design. The method further comprises during the simulating, using said breakpoints to pause the simulating at the defined intervals, and during each pause, comparing a measured value for the performance metric to the target value for the performance metric; and ending the simulation when a specified condition based on said comparing is met. In embodiments, when a difference between the measured value for the performance metric and the target value for the performance metric is within a preset tolerance, the pause is ended and the simulation continues.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.