Triple verification device and triple verification method
US11562177B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Nov 27, 2019 |
| Grant date | Jan 24, 2023 |
| Priority date | — |
| Expiry date | Sep 9, 2041 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06N3/048
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A triple verification method is provided. The triple verification method includes setting a triple having a source entity, a target entity, and a relation value between the source entity and the target entity by a setting unit, extracting a plurality of intermediate entities associated with the source entity and the target entity by the setting unit, defining a connection relation between the intermediate entity, the source entity, and the target entity and generating a plurality of connection paths connecting the source entity, the intermediate entity, and the target entity by a path generation unit, generating a matrix by embedding the plurality of connection paths into vector values by a first processing unit, calculating a feature map by performing a convolution operation on the matrix by a second processing unit, generating an encoding vector for each connection path by encoding the feature map by applying a bidirectional long short-term memory neural network (BiLSTM) technique by a third processing unit, and generating a state vector by summing the encoding vectors for each connection path by applying an attention mechanism and verifying the triple based on a similarity value…
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.