Memory device storing parity and memory system including the same
US11562803B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Apr 29, 2021 |
| Grant date | Jan 24, 2023 |
| Priority date | — |
| Expiry date | Apr 29, 2041 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C29/78
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A memory device includes a cell array including a plurality of pages and a control logic configured to control program and read operations of the cell array. The control logic controls the program and read operations to store first through N-th codewords in a first page among the pages and program a page parity corresponding in common to the first through N-th codewords to the first page in response to a program command for a page unit and to selectively read the first codeword among the first through N-th codewords in response to a read command for a sub-page unit, where N is an integer of at least 2. The first codeword includes first sub-page data and a first sub-parity corresponding thereto, and the first sub-parity includes information for correcting an error in the first sub-page data through error correction code (ECC) decoding independently performed on each codeword.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.