Method to improve CMOS device performance
US11562932B2 · kind B2 · utility
Assignees
Inventors
Key dates
| Filing date | Mar 20, 2018 |
| Grant date | Jan 24, 2023 |
| Priority date | — |
| Expiry date | Dec 8, 2039 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D84/8314
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A method for manufacturing a semiconductor device includes providing a substrate including a first device region and a second device region spaced apart from each other, forming a first oxide layer on the first device region and the second device region, forming a second oxide layer below the first oxide layer, forming a mask layer on the first oxide layer on the first device region while exposing the first oxide layer on the second device region, removing the first and second oxide layers on the second device region using the mask layer as a mask, removing the mask layer, and forming a gate oxide layer on the second device region. The thus formed gate oxide layer structure has improved quality and reliability.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.