Chip scale package
US11562952B2 · kind B2 · utility
0Cited by
2References
22Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Apr 30, 2021 |
| Grant date | Jan 24, 2023 |
| Priority date | — |
| Expiry date | Apr 30, 2041 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L2924/15173
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
The present disclosure relates to a chip scale package (CSP) comprising: a first set of CSP contact balls or bumps; a second set of CSP contact balls or bumps; and a channel routing region, the channel routing region being devoid of any CSP contact balls or bumps.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.