Method of manufacturing thin film transistor and display device including polishing capping layer coplanar with active layer
US11563126B2 · kind B2 · utility
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2References
12Claims
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Key dates
| Filing date | Jun 15, 2021 |
| Grant date | Jan 24, 2023 |
| Priority date | — |
| Expiry date | Jul 28, 2041 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10K59/1201
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A thin film transistor includes an active layer including a first portion having a first thickness and a second portion having a second thickness greater than the first thickness, a capping layer filling a thickness difference between the first portion and the second portion and arranged on the first portion, a gate insulating layer arranged on the capping layer, a gate electrode on the active layer, wherein the gate insulating layer and the capping layer are disposed between the gate electrode and the active layer, and a source electrode and a drain electrode connected to the active layer.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.