Clock skew calibration for time interleaved ADCS
US11563428B1 · kind B1 · utility
Assignee
Inventors
Key dates
| Filing date | Jun 22, 2020 |
| Grant date | Jan 24, 2023 |
| Priority date | — |
| Expiry date | Jun 22, 2040 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH03K5/1508
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
A method and apparatus for determining a set of cascading clock cycles, the method comprising inputting a set of phase changes of a set of clocks into a set of input circuits; wherein the set of phase changes are either falling phase changes or rising phase changes; wherein two phase changes of the set of clocks are fed into each input circuit of the set of input circuits, determining for each input circuit of the set of input circuits a duty cycle, storing the duty cycle for each input circuit of the input circuits in a set of duty cycles, calculating skew between the set of clocks using the duty cycles, and adjusting a delay to lower the skew between the set of clocks.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.