High performance phase locked loop for millimeter wave applications
US11563436B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Jul 13, 2022 |
| Grant date | Jan 24, 2023 |
| Priority date | — |
| Expiry date | Jul 13, 2042 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH03L7/1976
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
A phase lock loop (PLL) includes an input comparison circuit configured to compare a reference signal to a divided feedback signal and generate at least one charge pump control signal based thereupon. A charge pump generates a charge pump output signal in response to the at least one charge pump control signal. A loop filter is coupled to receive and filter the charge pump output signal to produce an oscillator control signal. An oscillator generates an output signal in response to the oscillator control signal, with the output signal divided by a divisor using divider circuitry to produce the divided feedback signal. Divisor generation circuitry is configured to change the divisor over time so that a frequency of the divided feedback signal changes from a first frequency to a second frequency over time.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.