Hammer refresh row address detector, and semiconductor memory device and memory module including the same
US11568917B1 · kind B1 · utility
Assignees
Inventors
Key dates
| Filing date | Oct 19, 2021 |
| Grant date | Jan 31, 2023 |
| Priority date | — |
| Expiry date | Oct 19, 2041 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C11/408
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A hammer refresh row address detector includes a control logic unit that receives a row address applied along with an active command, to increase a hit count stored in a corresponding entry when the row address is present in candidate aggressor row addresses stored in n entries. The control logic determines a candidate aggressor row address stored in an entry in which the hit count equals a threshold value to be a target aggressor row address. The control logic generates a victim row address adjacent to the target aggressor row address as a hammer refresh row address to accompany a hammer refresh command. The control logic increases the miss count value when the row address is not present in the candidate aggressor row addresses stored in the n entries and no hit count within the n entries is identical to the miss count value.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.