Memory circuit and method of operating same
US11568948B2 · kind B2 · utility
2Cited by
2References
20Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | May 13, 2021 |
| Grant date | Jan 31, 2023 |
| Priority date | — |
| Expiry date | May 13, 2041 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C17/16
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A memory circuit includes a non-volatile memory cell, a sense amplifier coupled to the non-volatile memory cell, and configured to generate a first output signal, and a detection circuit coupled to the sense amplifier and the non-volatile memory cell. The detection circuit is configured to latch the first output signal and disrupt a current path between the non-volatile memory cell and the sense amplifier.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.