Semiconductor package test method, semiconductor package test device and semiconductor package
US11568949B2 · kind B2 · utility
0Cited by
11References
17Claims
0Family size
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Key dates
| Filing date | Sep 11, 2020 |
| Grant date | Jan 31, 2023 |
| Priority date | — |
| Expiry date | Sep 15, 2040 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C2029/5606
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A method of testing a semiconductor package including a plurality of semiconductor chips includes sensing electrical signals respectively output from a plurality of semiconductor chip groups each representing a combination of at least two semiconductor chips among the plurality of semiconductor chips, obtaining amplitudes of electrical signals respectively output from the plurality of semiconductor chips based on the plurality of sensed electrical signals, and outputting a test result for the semiconductor package by using the plurality of obtained electrical signals.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.