Structure and formation method of chip package with through vias
US11569159B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Jun 4, 2020 |
| Grant date | Jan 31, 2023 |
| Priority date | — |
| Expiry date | Jun 4, 2040 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L2225/1058
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A package structure and a formation method of a package structure are provided. The method includes forming a conductive structure over a carrier substrate. The conductive structure has a lower portion and an upper portion, and the upper portion is wider than the lower portion. The method also includes disposing a semiconductor die over the carrier substrate. The method further includes forming a protective layer to surround the conductive structure and the semiconductor die. In addition, the method includes forming a conductive bump over the conductive structure. The lower portion of the conductive structure is between the conductive bump and the upper portion of the conductive structure.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.