Semiconductor memory device including wiring contact plugs
US11569171B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | May 26, 2021 |
| Grant date | Jan 31, 2023 |
| Priority date | — |
| Expiry date | May 26, 2041 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10B12/50
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A semiconductor memory device includes a substrate including a cell area and a peripheral area, a plurality of capacitors including a plurality of lower electrodes arranged in the cell area, a plurality of capacitor dielectric layers covering the plurality of lower electrodes, and an upper electrode on the plurality of capacitor dielectric layers, an etch stop layer covering the upper electrode, a filling insulation layer covering the etch stop layer and arranged in the cell area and the peripheral area, a plurality of wiring lines on the filling insulation layer, and a first wiring contact plug electrically connecting at least one of the plurality of wiring lines to the upper electrode. The upper electrode includes a first upper electrode layer covering the plurality of capacitor dielectric layers and including a semiconductor material and a second upper electrode layer covering the first upper electrode layer and including a metallic material.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.