Variable capacitance circuit for phase locked loops
US11569814B1 · kind B1 · utility
Assignee
Inventors
Key dates
| Filing date | Oct 15, 2021 |
| Grant date | Jan 31, 2023 |
| Priority date | — |
| Expiry date | Oct 15, 2041 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH03L7/0895
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
A variable capacitance circuit may operate a Metal Oxide Semiconductor (MOS) transistor or other semiconductor device to switch a capacitor in and out. Several circuits may be combined in a parallel network having offset bias voltages, such that the combined network may produce a variable capacitance over a large voltage range. The variable capacitance circuit may be incorporated into a phase locked loop (PLL) circuit where similar devices may be configured to produce a voltage reference as part of the PLL circuitry. Such a circuit may be immune to temperature, process, or voltage variances, since the current pulse magnitude times the low pass filter resistance times the sensitivity of a controlled voltage oscillator can be held constant.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.