Clock-error estimation for two-clock electronic device
US11573595B2 · kind B2 · utility
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9References
17Claims
0Family size
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Key dates
| Filing date | May 18, 2022 |
| Grant date | Feb 7, 2023 |
| Priority date | — |
| Expiry date | May 18, 2042 |
Classification
- Technology area (CPC Y)Emerging Cross-Sectional Technologies
- CPC primaryY02D10/00
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
An embodiment method is disclosed for deriving an estimation value of a clock-error for a slave clock, wherein the slave clock is set at a nominal slave period and outputs a sequence of slave clock signals at an actual slave period, and wherein a difference between the actual slave period and the nominal slave period is approximated by the estimation value of the clock-error.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.