Memory device for reducing resources used for training
US11574670B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Mar 9, 2022 |
| Grant date | Feb 7, 2023 |
| Priority date | — |
| Expiry date | Mar 9, 2042 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C2207/2254
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A memory device includes: first power pins in a first power area and configured to receive a first power voltage; data pins configured to transmit or receive data signals, the data pins being arranged in a first region and in a second region each including the first power area; control pins configured to transmit or receive control signals in the first region and in the second region; second power pins in a second power area between the first region and the second region and configured to receive a second power voltage different from the first power voltage; and ground pins in the second power area and configured to receive a ground voltage.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.