Clamp for power transistor device
US11574902B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Jan 31, 2019 |
| Grant date | Feb 7, 2023 |
| Priority date | — |
| Expiry date | Sep 4, 2039 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D89/819
- WIPO fieldElectrical machinery, apparatus, energy
- WIPO sectorElectrical engineering
Abstract
A system includes a clamp network coupled between an input and an output and configured to clamp a voltage between the input and the output to a first clamp voltage based on the presence of a trigger signal and to a second clamp voltage based on the absence of the trigger signal. The second clamp voltage is greater than the first clamp voltage and the first clamp voltage is less than a breakdown voltage of the power transistor device. A detector circuit is coupled to the input and the output. A power transistor device may also be coupled between the input and the output. The detector circuit is configured to detect a pulse signal at the input or the output while the power transistor device is off and to generate the trigger signal for a time interval based on detecting the pulse signal.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.