Semiconductor device including insulating patterns and method for forming the same
US11574915B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | May 24, 2021 |
| Grant date | Feb 7, 2023 |
| Priority date | — |
| Expiry date | Jul 20, 2041 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10B12/482
Abstract
A semiconductor device includes first bit lines disposed on a substrate. Buried contacts disposed among first bit lines and connected to the substrate are provided. Landing pads are disposed on the buried contacts. Second bit lines are disposed on a peripheral area of the substrate. Upper surfaces of the second bit lines and the landing pads are coplanar with each other. First insulating patterns are disposed among the second bit lines. Second insulating patterns are disposed among the landing pads. Cell capacitors connected to the landing pads are disposed. The first insulating patterns include an insulating layer different from at least one insulating layer of the second insulating patterns.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.