Semiconductor structure and operation circuit
US11574997B1 · kind B1 · utility
Assignee
Inventors
Key dates
| Filing date | Aug 2, 2021 |
| Grant date | Feb 7, 2023 |
| Priority date | — |
| Expiry date | Aug 2, 2041 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D62/378
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
A semiconductor structure including a substrate, a first well, a second well, a first doped region, a second doped region, a gate electrode, an insulating layer, a field plate, and a tunable circuit is provided. The first and second wells are formed on the substrate. The first doped region is formed in the first well. The second doped region is formed in the second well. The gate electrode is disposed over the substrate. The gate electrode, the first doped region, and the second doped region constitute a transistor. The insulating layer is disposed on the substrate and overlaps the gate electrode. The field plate overlaps the insulating layer and the gate electrode. The tunable circuit provides either a first short-circuit path between the field plate and the gate electrode, or a second short-circuit path between the field plate and the first doped region.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.