Patent · US Active

Gallium nitride transistors with source and drain field plates and their methods of fabrication

US11575036B2 · kind B2 · utility

0Cited by

1References

14Claims

0Family size

Assignee

Intel Corporation · US

Inventors

Han Wui Then · Portland, US
Stephan Leuschner · Lübeck, DE
Marko Radosavljevic · Portland, US
Sansaptak Dasgupta · Hillsboro, US

Key dates

Filing date	Sep 28, 2017
Grant date	Feb 7, 2023
Priority date	—
Expiry date	Dec 22, 2037

Classification

Technology area (CPC H)Electricity
CPC primaryH10D64/513
WIPO fieldBasic communication processes
WIPO sectorElectrical engineering

Abstract

Gallium nitride (GaN) transistors with source and drain field plates are described. In an example, a transistor includes a gallium nitride (GaN) layer above a substrate, a gate structure over the GaN layer, a source region on a first side of the gate structure, a drain region on a second side of the gate structure, the second side opposite the first side, a source field plate above the source region, and a drain field plate above the drain region.

Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.