Patent · US Active

Clocking system and a method of clock synchronization

US11575383B2 · kind B2 · utility

0Cited by

5References

10Claims

0Family size

Assignee

SKYECHIP SDN BHD · MY

Inventors

Chee Hak Teh · Kampung Bukit Kechil, MY
Yu Ying Ong · Ampang Jaya, MY
Wong Ging Yeon Mark · Teluk Tempoyak, MY
Tat Hin Tan · Bayan Lepas, MY
Soong Khim Chew · Teluk Tempoyak, MY

Key dates

Filing date	Feb 6, 2021
Grant date	Feb 7, 2023
Priority date	—
Expiry date	Feb 6, 2041

Classification

Technology area (CPC G)Physics
CPC primaryG11C2207/2254
WIPO fieldComputer technology
WIPO sectorElectrical engineering

Abstract

A device and method of clock synchronization for external memory interface. The device, and method, generating a clock output from a phase lock loop block via a sub-module clocking component; multiplexing the clock output through a global clock into different clock domains; clocking the data and an address or a command path by each clock domain; clocking the phase compensation FIFO by clock domain and clock phase alignment clock; generating the pointer for the phase compensation FIFO from central pointer generator block; and synchronizing the pointer of the adjacent intellectual property module with a parent intellectual property module.

Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.