Patent · US Active

Method and system for testing an integrated circuit

US11579191B2 · kind B2 · utility

1Cited by

5References

20Claims

0Family size

Assignee

TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LTD. · TW

Inventors

Chi-Che Wu · Taipei, TW
Tsung-Yang Hung · Dashulong, TW
Ming-Yih Wang · Jinshanmian, TW

Key dates

Filing date	Sep 16, 2020
Grant date	Feb 14, 2023
Priority date	—
Expiry date	Mar 26, 2041

Classification

Technology area (CPC G)Physics
CPC primaryG01R31/2834
WIPO fieldMeasurement
WIPO sectorInstruments

Abstract

A method is provided in the present disclosure. The method includes several operations: generating, by a processing unit, a mapping table associated with multiple scan chains and multiple shift cycles corresponding to multiple values stored in the scan chains in an integrated circuit; determining, based on the mapping table, at least one fail flip flop in the scan chains in response to the values outputted from the scan chains; and identifying at least one fault site corresponding to the at least one fail flip flop.

Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.