Semiconductor memory training method and related device
US11579810B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Mar 9, 2021 |
| Grant date | Feb 14, 2023 |
| Priority date | — |
| Expiry date | Mar 9, 2041 |
Classification
- Technology area (CPC Y)Emerging Cross-Sectional Technologies
- CPC primaryY02D10/00
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
The present application relates to a semiconductor memory training method and related devices, belonging to the technical field of semiconductors. The method comprises: obtaining a stored historical training result of a semiconductor memory, the historical training result comprising a historical expected delay value and a historical expected voltage; setting a delay threshold and a current training voltage range, the delay threshold being less than or equal to the historical expected delay value, the current training voltage range comprising the historical expected voltage; obtaining a current minimum delay value for the semiconductor memory under the historical expected voltage; and using the stored historical training result as a current training result of the semiconductor memory, if the current minimum delay value for the semiconductor memory under the historical expected voltage is no less than the delay threshold.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.