Verifying method for ECC circuit of SRAM
US11579969B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Jun 2, 2021 |
| Grant date | Feb 14, 2023 |
| Priority date | — |
| Expiry date | Jun 2, 2041 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C2029/0411
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A verifying method for an error checking and correcting (ECC) circuit of a static random-access memory (SRAM) is provided. The SRAM comprises a storage unit, an ECC circuit and a checking circuit. The ECC circuit receives an original data and an output first data. The checking circuit obtains a second data according to an error-injecting mask. The checking circuit performs a bit operation on the first data and the second data to obtain a third data. The checking circuit writes the third data into a test target area of the storage unit and the written data as a fourth data. The checking circuit reads the fourth data from the test target area. The ECC circuit obtains a fifth data and an error message according to the fourth data. The checking circuit obtains the bit error detection result according to the error message and the second data.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.