Methods and systems for implementing redundancy in memory controllers
US11579973B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Aug 31, 2021 |
| Grant date | Feb 14, 2023 |
| Priority date | — |
| Expiry date | Aug 31, 2041 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C29/765
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
The present disclosure relates to methods and systems for implementing redundancy in memory controllers. The disclosed systems and methods utilize a row of memory blocks, such that each memory block in the row is associated with an independent media unit. Failures of the media units are not correlated, and therefore, a failure in one unit does not affect the data stored in the other units. Parity information associated with the data stored in the memory blocks is stored in a separate memory block. If the data in a single memory block has been corrupted, the data stored in the remaining memory blocks and the parity information is used to retrieve the corrupted data.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.