Memory system, computing system, and methods thereof for cache invalidation with dummy address space
US11580029B2 · kind B2 · utility
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20Claims
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Key dates
| Filing date | Apr 6, 2021 |
| Grant date | Feb 14, 2023 |
| Priority date | — |
| Expiry date | Apr 13, 2041 |
Classification
- Technology area (CPC Y)Emerging Cross-Sectional Technologies
- CPC primaryY02D10/00
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A memory management system includes a cache invalidation logic configured to invalidate, based a cache invalidation event, cache entries within a cache memory by having each cache entry, of the cache entries within the cache memory, reference a respective dummy address from among dummy addresses within a dummy address space, wherein the cache memory is assigned to a memory, the memory has a memory address space associated therewith to provide access the memory, and each dummy address of the dummy addresses within the dummy address space is distinct from any address of the memory address space.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.