Display with hybrid oxide gate driver circuitry having multiple low power supplies
US11580905B2 · kind B2 · utility
0Cited by
9References
21Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | May 19, 2022 |
| Grant date | Feb 14, 2023 |
| Priority date | — |
| Expiry date | May 19, 2042 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG09G2330/028
- WIPO fieldAudio-visual technology
- WIPO sectorElectrical engineering
Abstract
A display may include an array of pixels that receive control signals from a chain of gate drivers. Each gate driver may include a logic sub-circuit and an output buffer sub-circuit. The output buffer sub-circuit may include depletion mode semiconducting oxide transistors with high mobility. The logic sub-circuit may include semiconducting oxide transistors, some of which can be depletion mode transistors and some of which can be enhancement mode transistors with lower mobility. The logic sub-circuit may include at least a carry circuit, a voltage setting circuit, an inverting circuit, a discharge circuit.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.