Memory sense amplifier trimming
US11581027B2 · kind B2 · utility
3Cited by
1References
20Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Dec 6, 2021 |
| Grant date | Feb 14, 2023 |
| Priority date | — |
| Expiry date | Dec 6, 2041 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C2029/4402
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A memory device, such as an MRAM memory, includes a memory array with a plurality of bit cells. The memory array is configured to store trimming information and store user data. A sense amplifier is configured to read the trimming information from the memory array, and a trimming register is configured to receive the trimming information from the sense amplifier. The sense amplifier is configured to receive the trimming information from the trimming register so as to operate in a trimmed mode for reading the user data from the memory array.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.