Sense amplification circuit and method of reading out data
US11581034B1 · kind B1 · utility
Assignee
Inventor
Key dates
| Filing date | Aug 8, 2022 |
| Grant date | Feb 14, 2023 |
| Priority date | — |
| Expiry date | Aug 8, 2042 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C2207/002
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
The present disclosure provides a sense amplification circuit and a method of reading out data, including: a first PMOS transistor; a first NMOS transistor; a second PMOS transistor; a second NMOS transistor; a first control MOS transistor configured to provide a bias voltage to the first PMOS transistor according to a control signal; a second control MOS transistor configured to provide the bias voltage to the second PMOS transistor according to the control signal; a first offset cancellation MOS transistor configured to electrically connect an initial bit line to a first complementary readout bit line according to an offset cancellation signal; and a second offset cancellation MOS transistor configured to electrically connect an initial complementary bit line to a first readout bit line according to the offset cancellation signal.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.