Adaptive read disturb algorithm for NAND storage accounting for layer-based effect
US11581058B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | May 17, 2021 |
| Grant date | Feb 14, 2023 |
| Priority date | — |
| Expiry date | May 17, 2041 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C29/4401
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A storage device includes 3D NAND including layers of multi-level cells. Test reads are performed by reading only LSB pages and reading layers in a repeating pattern of reading two and skipping two. A test read of a block is performed when its read count reaches a threshold. The counter threshold is updated according to errors detected during the test read such that the frequency of test reads increases with increase in errors detected. Counter thresholds according to errors may be specified in a table. The table may be selected as corresponding to a range of PEC values including the current PEC count of the 3D NAND. Each table further specifies a number of errors that will result in garbage collection being performed.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.