Etch profile control of gate contact opening
US11581218B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Mar 9, 2021 |
| Grant date | Feb 14, 2023 |
| Priority date | — |
| Expiry date | Apr 13, 2041 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D84/83
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A method comprises forming a gate structure between gate spacers; etching back the gate structure to fall below top ends of the gate spacers; forming a gate dielectric cap over the etched back gate structure; performing an ion implantation process to form a doped region in the gate dielectric cap; depositing a contact etch stop layer over the gate dielectric cap and an ILD layer over the contact etch stop layer; performing a first etching process to form a gate contact opening extending through the ILD layer and terminating prior to reaching the doped region of the gate dielectric cap; performing a second etching process to deepen the gate contact opening, wherein the second etching process etches the doped region of the gate dielectric cap at a slower etch rate than etching the contact etch stop layer; and forming a gate contact in the deepened gate contact opening.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.