Flexible impedance network system
US11581299B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Mar 12, 2020 |
| Grant date | Feb 14, 2023 |
| Priority date | — |
| Expiry date | Feb 10, 2041 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L2223/6655
- WIPO fieldTelecommunications
- WIPO sectorElectrical engineering
Abstract
Techniques and architecture are disclosed for a method for making a custom circuit comprising forming a common wafer template, selecting at least two elements of the common wafer template to be chosen elements, and adding at least one metal layer to interconnect the chosen elements to form a circuit. The common wafer template includes a plurality of transistors, a plurality of resistors, a plurality of capacitors, and a plurality of bond pads. Final circuit customization of the common wafer template is accomplished by adding at least one metal layer that forms interconnects to passive and active elements in the template in order to complete the circuit.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.