Integrated circuit device and method of fabricating the same
US11581333B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Jan 11, 2022 |
| Grant date | Feb 14, 2023 |
| Priority date | — |
| Expiry date | Jan 11, 2042 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L2225/06572
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
An integrated circuit device includes: a lower memory stack including a plurality of lower word lines located on a substrate, an upper memory stack located on the lower memory stack and including a plurality of upper word lines, at least one first lower interconnection layer extending in a horizontal direction at a first vertical level between the lower memory stack and the upper memory stack, and configured to be electrically connected to at least one lower word line selected from the plurality of lower word lines, a separate insulating film covering at least one first lower interconnection layer, and at least one first upper interconnection layer extending in the horizontal direction at a second vertical level higher than the upper memory stack, and configured to be electrically connected to at least one upper word line selected from the upper word lines.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.