Alternative data selector, full adder and ripple carry adder
US11581894B2 · kind B2 · utility
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1References
14Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | May 24, 2021 |
| Grant date | Feb 14, 2023 |
| Priority date | — |
| Expiry date | May 24, 2041 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH03K19/21
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
Alternative data selector, a full adder, and a ripple carry adder are disclosed. The alternative data selector includes: a NOR logic circuit configured to receive a selection signal and an inverted first input and generate an intermediate result; and an AND-OR-NOT logic circuit configured to receive the selection signal, a second input, and the intermediate result of the NOR logic circuit and generate an inverted output.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.