Analog-to-digital converter error shaping circuit and successive approximation analog-to-digital converter
US11581900B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Jun 17, 2021 |
| Grant date | Feb 14, 2023 |
| Priority date | — |
| Expiry date | Oct 9, 2041 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH03M7/165
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
Disclosed are an analog-to-digital converter error shaping circuit and a successive approximation analog-to-digital converter. The analog-to-digital converter error shaping circuit includes a decentralized capacitor array, a data weighted average module, a mismatch error shaping module, a control logic generation circuit, a digital filter and a decimator. The decentralized capacitor array includes two symmetrically arranged capacitor array units, each capacitor array unit includes a first sub-capacitor array of a high segment bit and a second sub-capacitor array of a low segment bit. The data weighted average module is configured to eliminate correlation between the first sub-capacitor array and an input signal, and the mismatch error shaping module is configured to eliminate correlation between the second sub-capacitor array and the input signal.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.