Sequence estimation system and method
US11582073B1 · kind B1 · utility
Assignee
Inventor
Key dates
| Filing date | Jan 31, 2022 |
| Grant date | Feb 14, 2023 |
| Priority date | — |
| Expiry date | Jan 31, 2042 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH04L25/03178
- WIPO fieldDigital communication
- WIPO sectorElectrical engineering
Abstract
A system comprising a processing circuitry configured to: obtain a first ordered sequence of symbols associated with a corresponding second ordered sequence of transmitted symbols and including one or more errors, the errors being discrepancies between given symbols of the first ordered sequence and corresponding symbols of the second ordered sequence; determine, for each symbol of the first ordered sequence of symbols, an estimated transmitted symbol, utilizing a Decision Feedback Equalizer (DFE); and determine if the estimated transmitted symbol of a given symbol of the first ordered sequence of symbols, satisfies a saturation threshold condition; and determine an error hypothesis identifying one or more of the errors by comparing the estimated transmitted symbol of at least one symbol of the first ordered sequence of symbols with one or more pairs of thresholds.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.