Photonic integrated circuit having improved electrical isolation between n-type contacts
US11585979B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Jan 7, 2020 |
| Grant date | Feb 21, 2023 |
| Priority date | — |
| Expiry date | Jun 23, 2041 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10H29/10
- WIPO fieldOptics
- WIPO sectorInstruments
Abstract
A photonic integrated circuit including first and second opto-electronic devices that are fabricated on a semiconductor wafer having an epitaxial layer stack including an n-type indium phosphide-based contact layer that is provided with at least one selectively p-type doped tubular-shaped region for providing an electrical barrier between respective n-type contact regions of the first and second opto-electronic devices that are optically interconnected by a passive optical waveguide that is fabricated in a non-intentionally doped waveguide layer including indium gallium arsenide phosphide, the non-intentionally doped waveguide layer being arranged on top of the n-type contact layer, wherein a first portion of the at least one selectively p-type doped tubular-shaped region is arranged underneath the passive optical waveguide between the first and second opto-electronic devices. An opto-electronic system including the photonic integrated circuit.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.