Pixel architecture, array substrate and display apparatus
US11586086B2 · kind B2 · utility
Assignees
Inventors
Key dates
| Filing date | Aug 21, 2020 |
| Grant date | Feb 21, 2023 |
| Priority date | — |
| Expiry date | Aug 21, 2040 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG09G2310/0297
- WIPO fieldAudio-visual technology
- WIPO sectorElectrical engineering
Abstract
A pixel architecture includes sub-pixels, gate lines extending in first direction and data lines. Two gate lines are provided between every two adjacent rows of sub-pixels. Each data line includes first extension portions extending in first direction and second extension portions extending in second direction intersecting the first direction. The gate lines and the data lines define pixel regions each being provided with two sub-pixels arranged in the first direction therein. Every two adjacent first extension portions and a second extension portion connected between the two first extension portions constitute a projection portion accommodating at least one pixel region. All sub-pixels in each projection portion are coupled to the same data line to receive data voltage signals with the same voltage polarity. Sub-pixels in two adjacent projection portions in the second direction are coupled to two adjacent data lines to receive data voltage signals with opposite voltage polarities.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.