Clock generator with noise rejection circuit
US11586238B1 · kind B1 · utility
0Cited by
8References
18Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Dec 15, 2021 |
| Grant date | Feb 21, 2023 |
| Priority date | — |
| Expiry date | Dec 15, 2041 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH03K2005/00078
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
A clock generator includes an input coupled to receive an input clock signal from a first clock source, and a noise rejection circuit configured to provide an output clock signal based on the input clock signal. The noise rejection circuit includes an event generator having a digital counter circuit. The event generator is configured to generate a first event signal based on a count value of the digital counter circuit, in which the noise rejection circuit is configured to produce an edge on the output clock signal in response to both the event signal and a state of the input clock signal.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.