System, device and method for accessing device-attached memory
US11586543B2 · kind B2 · utility
0Cited by
5References
20Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Jul 20, 2021 |
| Grant date | Feb 21, 2023 |
| Priority date | — |
| Expiry date | Jul 20, 2041 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F2212/621
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A device connected to a host processor via a bus includes: an accelerator circuit configured to operate based on a message received from the host processor; and a controller configured to control an access to a memory connected to the device, wherein the controller is further configured to, in response to a read request received from the accelerator circuit, provide a first message requesting resolution of coherence to the host processor and prefetch first data from the memory.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.